Increasing demand for large power ratings and physically limited maximum current density of semiconductor devices have made a parallel connection of semiconductors an attractive approach for high power applications. For example, a parallel connection of insulated gate bipolar transistors (IGBTs) is a widely used solution in high power converters.
However, the current through the parallel connection may not distribute evenly between the parallel-connected switching devices. Current imbalances may occur during the on-state (stationary operation) and/or during commutation transients (dynamic operation). If the currents are not balanced, the stresses of the switching devices may also be unbalanced. Stresses may concentrate on a particular switching device or particular switching devices.
In order to achieve a stationary balance of the currents of parallel-connected switching devices, various approaches have been developed. Most of these approaches are based on derating and/or selecting the semiconductors. However, derating the semiconductors (see references [1] and [2] below) may cause a reduced utilization of the silicon die and, therefore, higher costs. Further, the semiconductor dies may have to be selected in order to ensure the operation of each die within the safe operating area defined in the data sheet. Picking semiconductors (see references [1] and [2] below) according to certain device parameters (e.g. gate-emitter threshold voltage, switching times, on-state voltage, etc.) may cause additional costs in the selection procedure and, thus, complicate service, maintenance and converter part replacement.
Current may also be balanced by an active adjustment control of the maximum value of the gate-emitter voltage (see reference [3] below) on the basis of the collector current measurement. However, this approach may be too expensive to be implemented in a commercial converter due to the required measurement of device currents. Furthermore, the active control of the maximum value of the gate-emitter voltage may show low performance due to the coupling of the stationary and dynamic balancing of the semiconductors.
Current balancing may also be achieved through symmetrical design (including mechanical layout) of the converter structures regarding stray inductances (see references 4-6 below). A drawback of this approach is that a symmetric implementation of the converter may generate higher development and manufacturing costs, and add limitations to the mechanical layout and design of the converter.
All of the above-mentioned measures may cause an additional expense of material, development costs as well as manufacturing costs, and make service complicated and difficult.